A pixel pipeline refers to elements of a computer windowing system that process pixel information for display. In FIG. 1, a pixel pipeline 100 according to the prior art for a computer windowing system is schematically illustrated. The prior art pipeline 100 includes a Graphics Processing Unit (GPU) 110, system memory 102, Video Random Access Memory (VRAM) 104, and output hardware 106, which are all components of the computer system. Typically, VRAM refers to any kind of random access memory (regardless of the actual type) that is coupled directly to the GPU so it can be accessed quickly (typically in an arrangement that makes VRAM much faster for the GPU to access than a Central Processing Unit (CPU)).
The system memory 102 has backing stores 120 and 122, and the VRAM has an assembly buffer 130. The output hardware 106 includes a frame buffer 140, scan-out hardware 150, and a display panel 160. As is known in the art, the backing stores 120 and 122 receive information from applications and the operating system of the computer system. The frame buffer 140 holds the complete bit-mapped image that is eventually sent to the display 160 by the scan-out hardware 150.
In the art, pixels can be stored with various color depths, including 1-bit monochrome, 4-bit palletized, 8-bit palletized, 16-bit Highcolor, and 24-bit Truecolor, for example. An additional alpha component can also be used for pixel transparency. In 24-bit Truecolor, for example, each of the color components Red, Green, and Blue is represented by 8-bits in the RGB color space so that the color depth for the pixel is represented by a total of 24-bits. Each color component Red, Green, and Blue has 28 or 256 levels of color and can be combined to give a total of 16,777,216 mixed colors (256×256×256).
To display images on the display panel 160 with the prior art pixel pipeline 100, the operating system and applications of the computer system store pixel information in the backing stores 120, 122. Typically, the operating system and applications use only 8-bits per component for the pixel information, and the backing stores 120 and 122 are configured to store only 8-bits per component. The GPU 110 composites the pixel information stored in the backing stores 120 and 122 into an assembly buffer 130 of the VRAM 104. When compositing, the GPU 110 formats the pixel information in the same eventual format of the frame buffer 140 Typically, the frame buffer 140 is configured for 8-bits per component, although graphics cards are known in the art that offer greater than 8-bit frame buffers.
The prior art pixel pipeline 100 for the computer windowing system handles pixel information with less accuracy due to the low color depth available for the compositing and processing of pixel information for display 160. The subject matter of the present disclosure is directed to overcoming or at least reducing this and other limitations associated with the prior art pixel pipeline.